Reconfigurable switched-capacitor voltage converter circuit, integrated circuit (ic) chip including the circuit and method of switching voltage on chip

ABSTRACT

A configurable-voltage converter circuit that may be CMOS and an integrated circuit chip including the converter circuit and method of operating the IC chip and circuit. A transistor totem, e.g., of 6 or more field effect transistors, PFETs and NFETs, connected (PNPNPN) between a first supply (V in ) line and a supply return line. A first switching capacitor is connected between first and second pairs of totem PN FETs pair of transistors. A second switching capacitor is connected between the second and a third pair of totem FETs. A configuration control selectively switches both third FETs off to float the connected end of the second capacitor, thereby switching voltage converter modes.

FIELD OF THE INVENTION

The present invention is related to voltage conversion techniques and,more particularly, to switched capacitor voltage converters and methodsfor use in integrated circuit devices.

BACKGROUND DESCRIPTION

Especially for complex Integrated Circuit (IC) chips and IC chips witharrays with a large number of devices, device leakages can overwhelmchip power be. A general application of leakage reduction techniquesimpairs performance and has been equally unpalatable. Accordingly, somedesigns use multiple supplies or a variable supply to selectively reducesupply voltage, e.g., supply one voltage during memory access and asecond, lower voltage when memory cells are not being accessed.

Thus, some higher performance chips use on-chip voltage converters,e.g., switched-capacitor circuits, to reduce higher chip supply voltagesto a level suitable for high performance circuit operation. State of theart switched-capacitor circuits inherently enable very high efficiencyfor ratioed conversion. For example, a 2:1 down conversion (0.5) hasdemonstrated at 90% efficiency. Such a voltage converter enables muchhigher supply voltage delivery to the chip for powering lower voltagecircuit, e.g., providing a 2.0V supply to the chip may be converted downto 1.0V on-chip for 1V circuits. Linear regulators, which have been usedfor voltage conversion at ratios above 0.5, also achieve >90% efficiencyfor conversion at the higher performance end of the output voltagerange, e.g., 1.3V to >1.2V conversion. However, efficiency falls offdramatically at the lower end of the output voltage range, e.g., ˜50%for 1.3V->0.7V conversion and below.

Thus, there is a need for a high efficiency voltage converter foron-chip voltage conversion that provides uniform efficiency across awide conversion range; and more particularly, a variable conversionratio on-chip voltage converter, and especially a variable voltageswitched-capacitor converter, that exhibits a high efficiency even atthe lower end of the voltage conversion range.

SUMMARY OF THE INVENTION

A feature of the invention is improved power efficiency in downconverting on-chip supply voltages;

Another feature of the invention is a switchable voltage supply,supplying low-voltage performance circuits with a reduced chip voltage;

Yet another feature of the invention is reduced chip supply switchingnoise;

Yet another feature of the invention is a switchable voltage supply,supplying low-voltage performance circuits with a reduced chip voltage,while improving power convertion efficiency and chip supply switchingnoise.

The present invention relates to a configurable-voltage convertercircuit that may be CMOS and an integrated circuit chip including theconverter circuit and method of operating the IC chip and circuit. Atransistor totem, e.g., of 6 or more field effect transistors, PFETs andNFETs, connected (PNPNPN) between a first supply (V_(in)) line and asupply return line. A first switching capacitor is connected betweenfirst and second pairs of totem PN FETs pair of transistors. A secondswitching capacitor is connected between the second and a third pair oftotem FETs. A configuration control selectively switches both third FETsoff to float the connected end of the second capacitor, therebyswitching voltage converter modes.

Embodiments of the invention include:

A method of configuring on-chip supply voltage being supplied to one ormore chip circuits, said method comprising: selecting a first voltagesupply mode; floating one side of a first capacitor in a pair of seriesconnected capacitors, the other side of said first capacitor beingconnected to a first side of a second capacitor of the series connectedpair; alternately switching opposite sides of said second capacitor to avoltage supply output (V_(out)), one side of said second capacitor beingalternately switched between a first supply voltage and said voltagesupply output, the other side of said second capacitor being alternatelyswitched between a second supply voltage and said voltage supply output,said voltage supply output supplying a first output voltage; selecting asecond voltage supply mode; alternately floating and coupling said oneside of said first capacitor to said first supply voltage andsimultaneously switching the other side of said second capacitor to saidvoltage supply output when said one side is floating, said first side ofsaid second capacitor being alternately switched in and out to saidvoltage supply output, the other side of said second capacitor beingalternately switched between said second supply voltage and said voltagesupply output, said voltage supply output supplying a second outputvoltage; and waiting to reselect said first voltage supply mode.

In this embodiment in said first voltage supply mode alternatelyswitching said opposite sides comprises: floating one side of a firstcapacitor in a pair of series connected capacitors, the other side ofsaid first capacitor being connected to a first side of a secondcapacitor of the series connected pair; asserting a first clock;coupling said first side of said second capacitor to said first supplyvoltage responsive to said first clock; coupling the other side of saidsecond capacitor to said supply voltage output responsive to said firstclock; asserting a second clock, said first clock and said second clocknot overlapping; coupling said first side of said second capacitor tosaid supply voltage output responsive to said second clock; coupling theother side of said second capacitor to said second supply voltageresponsive to said second clock; and returning to asserting said firstclock.

In said second voltage supply mode alternately floating and couplingsaid one side and alternately switching said opposite sides comprises:asserting said first clock; coupling said one side of said firstcapacitor to said first supply voltage responsive to said first clock;coupling said other side of said second capacitor to said voltage supplyoutput responsive to said first clock; asserting a second clock, saidone side of said second capacitor being floated; coupling said otherside of a said first capacitor to said voltage supply output responsiveto said second clock; coupling said other side of said second capacitorto said second supply voltage responsive to said second clock; andreturning to asserting said first clock. The first capacitor may beconnected between a pair of FETs and floating said one side of saidfirst capacitor comprises gating both FETs off. Floating said one sideof said first capacitor further comprises gating on an FET shorting theopposite ends of both off FETs. The chip may be a CMOS chip, where saidpair of FETs is a PFET and an NFET in a FET totem including alternatePFETs and NFETs; said other side of said first capacitor and said firstside of a second capacitor of the series connected capacitor pair beingconnected between a second PN FET pair; and said other side of saidsecond capacitor being connected between a second PN FET pair. Assertingsaid first clock may turn on totem PFETs with asserting said secondclock turning on totem NFETs, the first PN FET pair being gated by saidfirst clock and said second clock when said second mode is selected. Thesecond supply voltage may be a supply return for said first supplyvoltage (V_(in)).

Another embodiment is a method of configuring on-chip supply voltagebeing supplied to one or more chip circuits, said method comprising:selecting a first voltage supply mode; floating one side of a firstcapacitor in a pair of series connected capacitors, the other side ofsaid first capacitor being connected to a first side of a secondcapacitor of the series connected pair; and while said first voltagesupply mode is selected, asserting a first clock; coupling said firstside of said second capacitor to a first voltage supply line responsiveto said first clock; coupling the other side of said second capacitor toan on-chip supply voltage output (V_(out)) responsive to said firstclock; asserting a second clock, said first clock and said second clocknot overlapping; coupling said first side of said second capacitor tosaid on-chip supply voltage output responsive to said second clock;coupling the other side of said second capacitor to a second voltagesupply line responsive to said second clock; and returning to assertsaid first clock.

This embodiment further comprises: selecting a second voltage supplymode; and while said second voltage supply mode is selected, assertingsaid first clock; coupling said one side of said first capacitor to saidfirst voltage supply line responsive to said first clock; coupling saidother side of said second capacitor to said on-chip supply voltageoutput responsive to said first clock; asserting a second clock;coupling said one side of a said first capacitor to said on-chip supplyvoltage output responsive to said second clock; coupling said other sideof said second capacitor to said second voltage supply line responsiveto said second clock; and returning to assert said first clock. Thefirst voltage supply mode may be a 2:1 configuration mode, said secondvoltage supply mode may be a 3:1 configuration mode and upon a nextselection of said 2:1 mode, said method further comprising returning tofloat said one side of said first capacitor. The first capacitor isconnected between a pair of FETs and floating said one side of saidfirst capacitor comprises gating both FETs off. One of said firstvoltage supply line and said second voltage supply line may be a supplyreturn line and the other may be a chip supply (V_(in)), floating saidone side of said first capacitor further comprises gating on an FETshorting the opposite ends of both off FETs, and V_(in):V_(out) may beselectable as 2:1 or 3:1. The chip may be a CMOS chip, with said pair ofFETs being a PFET and an NFET in a FET totem including alternate PFETsand NFETs; said other side of said first capacitor and said first sideof a second capacitor of the series connected capacitor pair beingconnected between a second PN FET pair; and said other side of saidsecond capacitor being connected between a second PN FET pair. Assertingsaid first clock turns on totem PFETs and asserting said second clockturns on totem NFETs, the first PN FET pair being gated by said firstclock and said second clock when said second mode is selected. Thesecond supply voltage line may be said supply return for said firstsupply voltage line (V_(in)).

Another embodiment is a method of configuring on-chip supply voltagebeing supplied to one or more CMOS chip circuits, said methodcomprising: selecting a first voltage supply mode; floating one side ofa first capacitor in a pair of series connected capacitors connected toa field effect transistor (FET) totem connected between a first supply(V₁) and a second supply (V₂), the other side of said first capacitorbeing connected to a first side of a second capacitor of the seriesconnected pair, said one side being connected between a first PFET andNFET (PN FET) totem pair, said other side and said first side beingconnected between a second PN FET totem pair and the opposite side ofsaid second capacitor being connected between a third PN FET totem pair;alternately turning PFETs off and on and NFETs on and off in the secondand third PN FET totem pair, said second and third PN FET totem pairsalternately switching opposite sides of said second capacitor to avoltage supply output (V_(out)); selecting a second voltage supply mode;alternately turning PFETs off and on and NFETs on and off in the first,second and third PN FET totem pairs, said first PN FET totem pairalternately floating and coupling said one side of said first capacitorto V₁, and said second and third PN FET totem pairs simultaneouslyalternately switching said other side of said second capacitor toV_(out) when said one side is floating, said second and third PN FETtotem pairs alternately switching opposite sides of said secondcapacitor to V_(out); and waiting to reselect said first voltage supplymode.

In this embodiment in said first voltage supply mode, alternatelyswitching said opposite sides may comprise: in a first half cycle PFETsin both said the second and third PN FET totem pair being switched on,said PFET in said second PN FET totem pair switching said first side ofsaid second capacitor to V₁, and said PFET in said third PN FET totempair switching said opposite side of said second capacitor to V_(out),the corresponding NFETs in both pair being off; and in a second halfcycle by switching PFETs off and NFETs on, on NFETs switching said firstside of said second capacitor to V_(out) and said other side of saidsecond capacitor to V₂. Floating one side in said first voltage supplymode may comprise: shorting said first PN FET pair; and holding off boththe PFET and NFET in said first PN FET pair, said first side beingconnected between said PFET and NFET. V₁ may be V_(in), V₂ may be groundand shorting said first PN FET pair comprises turning on a shunting PFETin parallel with said first PN FET pair.

Alternately switching said opposite sides in said first voltage supplymode may comprise: asserting a PFET clock low, an NFET clock being lowwhile said PFET clock is asserted, said PFET in said second PN FET paircoupling said first side of said second capacitor to one side of saidshunt PFET, said PFET in said third PN FET pair coupling said other sideof said second capacitor to said V_(out); driving said PFET clock high;asserting said NFET clock high, said NFET in said second PN FET paircoupling said first side of said second capacitor to V_(out), said NFETin said third PN FET pair coupling the other side of said secondcapacitor to said supply return; driving said NFET clock low; andreturning to asserting said PFET clock low. Alternately floating andcoupling said one side of said first capacitor in said second voltagesupply mode may comprise: turning said shunting PFET off; and passingsaid PFET clock through a PFET clock gate to the gate of said PFET insaid first PN FET pair and said NFET through an NFET clock gate to thegate of said NFET in said first PN FET pair. V₁ may be ground, V₂ may beV_(in), shorting said first PN FET pair comprises turning on a shuntingNPFET in parallel with said first PN FET pair, and V_(in):V_(out) may beselectable as 2:1 in said first voltage supply mode or 3:1 in saidsecond voltage supply mode.

Yet another embodiment is a method of configuring on-chip supply voltagebeing supplied to one or more CMOS chip circuits, said methodcomprising: asserting a configuration select in a first state, saidfirst state selecting a first voltage supply mode; turning a shuntingfield effect transistor (FET) on, said shunting FET shorting a firstPFET and NFET pair (PN FET pair) in a FET totem connected between afirst supply voltage (V₁) and a second supply voltage (V₂), one side ofa first capacitor in a pair of series connected capacitors connectedbetween the PFET and NFET in said first PN FET pair; blocking a PFETclock and an NFET clock to said first PN FET pair, both the PFET andNFET in said first PN FET pair being held off, said one side of saidfirst capacitor floating; switching on PFETs in said the second andthird PN FET totem pair in a first half cycle, said PFET in said secondPN FET totem pair switching said first side of said second capacitor toV₁, and said PFET in said third PN FET totem pair switching the oppositeside of said second capacitor to V_(out), the corresponding NFETs inboth pair being off; switching said PFETs off in a second half cycle andNFETs on, on NFETs switching said first side of said second capacitor toV_(out) and said other side of said second capacitor to V₂; returning toswitching on PFETs until said configuration select is asserted in asecond state, and when asserted in said second state a second voltagesupply mode has been selected; and then turning off said shunting FET;passing said PFET clock and said NFET clock to said first PN FET pair,both the PFET and NFET in said first PN FET pair being gated on by arespective clock; switching on PFETs in the first, second and third PNFET totem pairs in a first half cycle, said PFET in said first PN FETtotem pair switching said one side of said first capacitor to V₁, andsaid PFET in said third PN FET totem pair switching the opposite side ofsaid second capacitor to V_(out), the corresponding NFETs in said first,second and third PN FET totem pairs being off; switching said PFETs offin a second half cycle and NFETs on, on NFETs switching said first sideof said second capacitor to V_(out) and said other side of said secondcapacitor to V₁; and returning to switching on PFETs in all three PN FETtotem pairs until said first voltage supply mode is reselected. V₁ maybe V_(in), V₁ may be ground, and V_(in):V_(out) may be selectable as 2:1in said first voltage supply mode or 3:1 in said second voltage supplymode.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing and other objects, aspects and advantages will be betterunderstood from the following detailed description of a preferredembodiment of the invention with reference to the drawings, in which:

FIG. 1 shows an example of a basic, switched-capacitor, voltageconverter circuit for providing a reduced on-chip supply voltage from ahigher, chip supply voltage;

FIGS. 2A-C show an example of operation of, and a timing diagram for,the voltage converter circuit dividing supply voltage V_(in), byalternately switching the charge on capacitor;

FIG. 3 shows an example of a 3:1 switched-capacitor, multi-voltageconverter circuit;

FIGS. 4A-B show an example of a preferred switched-capacitor,configurable-voltage converter circuit and timing, according to apreferred embodiment of the present invention;

FIG. 5 shows a graphic example of efficiency of the preferredswitched-capacitor, configurable-voltage converter circuit for V_(out)in both 3:1 mode and 2:1 mode;

FIGS. 6A-B show an example of the clock select circuits;

FIG. 7 shows another example of a preferred switched-capacitor,configurable-voltage converter circuit;

FIG. 8 shows an example of a of an Integrated Circuit (IC) chip with oneor more circuits powered by a preferred switched-capacitor,configurable-voltage converter circuit.

DESCRIPTION OF PREFERRED EMBODIMENTS

Semiconductor technology and chip manufacturing advances have resultedin a steady decrease of chip feature size to increase on-chip circuitswitching frequency (circuit performance) and the number of transistors(circuit density). Density has increased as a result ofshrinking/reducing overall device or field effect transistor (FET) sizeby reducing feature sizes and, correspondingly, device minimumdimensions. A typical shrink includes horizontal dimensions (e.g.,minimum channel length) and vertical dimensions, e.g., channel layerdepth, gate dielectric thickness, junction depths and etc. Smallerdevice features have improved device performance and reduced deviceoperating conditions, i.e., chip and correspondingly, device supplyvoltages and voltage swings.

Generally, all other factors being constant, the active power consumedby a given logic unit increases linearly with switching frequency (f),i.e., with performance. Also, higher operating frequency requires highercurrent (I) to switch loads faster. Thus, not withstanding the decreaseof chip supply voltage (V), chip power (P=VI) consumption has increasedas well. Both at the chip and system levels, a natural result of thisincrease in chip power is escalated cooling and packaging costs. For lowend systems (e.g., handhelds, portable and mobile systems), wherebattery life is crucial, reducing net power consumption is important.However, such a power reduction must come without degrading chip/circuitperformance below acceptable levels.

To minimize semiconductor circuit power consumption while maximizingperformance, most integrated circuits (ICs) are made in the well-knowncomplementary insulated gate FET technology known as CMOS. A typicalCMOS circuit includes paired complementary devices, i.e., an n-type FET(NFET) paired with a corresponding p-type FET (PFET), usually gated bythe same signal and, typically, driving a capacitive load. Ideally, whenthe gate of a NFET is below some positive threshold voltage (V_(T)) withrespect to its source, the NFET is off, i.e., the switch is open. AboveV_(T), the NFET is on conducting current, i.e., the switch is closed.Similarly, a PFET is off when its gate is above its V_(T), i.e., lessnegative, and on below V_(T).

A CMOS inverter, for example, is a PFET and NFET pair that are seriesconnected between a power supply voltage (V_(dd)) and ground (GND). Bothare gated by the same input and both drive the same output, more orless, a purely capacitive load. The PFET pulls the capacitive load highand the NFET pulls the load low at opposite input signal states. Sincethe pair of devices have operating characteristics that are,essentially, opposite each other, when one device (e.g., the NFET) is onand conducting (modeled simply as a closed switch), the other device(the PFET) is off, not conducting (ideally modeled as an open switch)and, vice versa. Thus, there is no static or DC current path in an idealCMOS circuit; ideal CMOS circuits use no static or DC power; and onlyconsume transient power from current charging and discharging capacitiveloads. Coincidentally, most noise on chip supply lines is switchingnoise from transient current switching the loads.

At chip level, supply switching currents through supply line resistancesand parasitic inductance can generate significant line noise at the chippower pins and/or pads, e.g., several hundred millivolt (mV) spikes on aone volt (1V) supply line. These current spikes waste power, impaircircuit operation, reduce performance, and may cause sporadic errorsthat are difficult to locate and diagnose. Without changing chip power,chip supply currents can be reduced by increasing chip supply voltageabove on-chip operating supply voltage. However, high performancecircuits normally operate at maximum tolerable supply voltage, wherehigher supply voltages may cause permanent circuit damage.

Moreover, in practice, typical FETs are much more complex than switchesand transient power for circuit loads accounts for only a portion ofCMOS chip power consumption. FET drain to source current (DC current andso, DC power consumed) is dependent upon circuit conditions and devicevoltages. Especially since device V_(T) is directly proportional to gatedielectric thickness, as FET features (including gate dielectricthickness) shrink, off FETs conduct what is known as subthresholdcurrent, i.e., at gate biases below threshold for NFETs and above forPFETs. Further, for a particular device, subthreshold current increasesexponentially with the magnitude of the device's drain to source voltage(V_(ds)) and reduces exponentially with the magnitude of the device'sV_(T). This is especially true in what is known as partially depleted(PD) or fully depleted (FD) silicon on insulator (SOI) technologies,where subthreshold leakage has been shown to increase dramatically, suchthat it may be the dominant source of leakage. Additional deviceleakages including gate leakages (i.e., gate to channel, gate to sourceor drain and gate induced drain leakage (GIDL)) and source/drainjunction leakages also contribute to static power.

When multiplied by the millions and even billions of devices on a stateof the art SRAM processor cache, for example, even one hundred picoAmps(100 pA) of leakage in each of a eight million cells results in chipleakage on the order of eight hundred milliAmps (800 mA). Thus, as FETfeatures have shrunk, these leakage sources have become more prominent.Generally, approaches to resolving these device problems have been toincrease device V_(T) to mitigate subthreshold leakage, or to reducesupply voltage. Especially for complex chips and arrays with a largenumber of devices, device leakage (both gate and subthreshold) chipleakage power can be overwhelming, but general application of leakagereduction techniques impairs performance and has been equallyunpalatable. Accordingly, some designs use multiple supplies or avariable supply to selectively reduce supply voltage, e.g., supply onevoltage during memory access and a second, lower voltage when memorycells are not being accessed.

FIG. 1 shows an example of a basic, switched-capacitor, voltageconverter circuit 50 for providing a reduced (2:1) on-chip supplyvoltage (V_(out)) from a higher, chip supply voltage (V_(in)). Thecircuit includes four FETs in a totem or push-pull arrangement betweenV_(in), and a second supply voltage or supply return (ground (GND)). TheFET totem of this example includes two NFETs 52N, 54N and two PFETs 52P,54P, and switches a single capacitor 56 with capacitance C. The NFETs52N, 54N are driven by a first or NFET phase (Φ) and the PFETs 52P, 54Pare driven by a second or PFET, in-phase non-overlapping phase (Φ*) withan operating or switching frequency (f). Each PN pair of devices, 52N,52P and 54N, 54P, drive one end of the capacitor 56 and PFET 52P andNFET 54N drive the output 58.

FIGS. 2A-C show an example of operation of, and a timing diagram for,the voltage converter circuit 50 for dividing supply voltage V_(in), byalternately switching the charge on capacitor 56. Ideally, in acompletely efficient (100%) down conversion for this 2:1 voltageconverter circuit 50, 2V_(out)=V_(in); or, V_(out)=½V_(in). In practice,however, there is some inherent inefficiency (Δ), whereΔ=½V_(in)−V_(out). Voltage converter efficiency, therefore, is 1−Δ.

When both Φ and Φ* transition low 60, both NFETs 52N, 54N are off andboth PFETs 52P, 54P are on, and the loop/output current (I_(load1)) 62is the PFET source to drain current. Since, I=CdV/dt, for a givenswitching frequency f, dV/dt≈V_(in)Δf and I_(load1)≈CV_(in)Δf.Similarly, when both Φ and Φ* transition high 64, both PFETs 52P, 54Pare off and both NFETs 52N, 54N are on, the loop/output current(I_(load2)) 66 is the NFET source to drain current, and again,I_(load2)≈CV_(in)Δf. Thus, at steady state,I_(load)=I_(load1)+I_(load2)≈2CV_(in)Δf, and V_(C)≈V_(out)=½V_(in)(1−Δ).

FIG. 3 shows an example of a somewhat more complex, switched-capacitor,multi-voltage converter circuit 70, again in an FET totem arrangement,substantially similar to the arrangement for switched-capacitor, 2:1voltage converter circuit 50 of FIGS. 1A-C. In this example, themulti-voltage converter circuit 70 includes six FETs, three NFETs 72N,74N, 76N and three PFETs 72P, 74P, 76P, driving two capacitors 78, 80,connected 82 between NFET 74N and PFET 74P. In this example, usingsubstantially the same analysis, it can be shown that the two downconverted voltage outputs are a 3:1 down converted output 84(V_(out3:1)≈⅓V_(in)) and a 3:2 down converted output 86(V_(out3:2)≈⅔V_(in)) of V_(in) 88 with an inherent efficiency of (1-2Δ),where Δ=⅓V_(in)−V_(out3:1). Providing a single circuit with a selectable2:1 or 3:1, stepped down voltages from both of these switched-capacitor,voltage converter circuits 50, 70, requires additional logic and voltageswitching capability, e.g., a pass gate multiplexor, that may introduceadditional circuit loss, i.e., additional inefficiency.

FIGS. 4A-B show an example of a preferred switched-capacitor,configurable-voltage converter circuit 100 and timing, according to apreferred embodiment of the present invention. In this example, thepreferred configurable-voltage converter circuit 100 includesconfigurable totem arrangement between a first voltage (V₁) and a secondvoltage (V₂), a supply voltage (V_(in)) 102 and supply return (ground(GND)) in this example, and a configuration control 104. Theconfigurable totem arrangement includes six FETs, three NFETs 106N,108N, 110N and three PFETs 106P, 108P, 110P and two switched capacitors112, 114, e.g., 2 nanoFarads (2 nF). The switched capacitors 112, 114are connected to each other 116 between PN FET pair 108N, 108P and atopposite ends 118, 120 between PN FET pairs 106N, 106P and 110N, 110P.The bottom NFETs 106N, 108N and PFETs 106P, 108P are driven directly byin-phase non-overlapping phases (Φ, Φ*), e.g., with a switchingfrequency f=200 MegaHertz (200 MHz).

In this example, the configuration control 104 is connected between thesupply 102 and an intermediate node 122 at the top PN pair of FETs,110N, 110P. The configuration control 104, selectively blocks or passesthe in-phase non-overlapping phases (Φ, Φ*) to the top PN pair FET, NFET110N and PFET 110P, depending on whether the configurable-voltageconverter circuit 100 is configured 2:1 or 3:1 mode, respectively. Amode select signal (VCONFIG) 124 passes through a level shifter 126 toprovide a configuration selection signal (CONFIG) 124′. The preferredconfigurable-voltage converter circuit 100 provides a single selectedoutput voltage (V_(out)) at the intermediate node 122 between the bottomtwo PN FET pairs 106N, 106P and 108N, 108P.

In this example, CONFIG 124, 124′ low selects 2:1 mode (V_(in), 102 toV_(out) 128) or, high selects 3:1 mode. A PFET 130 connected between thesupply 102 and the intermediate node 122 is gated by CONFIG 124′. Thelevel shifter 126 passes CONFIG 124′ to a pair of clock select circuits132, 134. The clock phases (Φ, Φ*) are in phase, but non-overlapping toprevent orthogonalities, where both PFETs 106P, 108P, 110P and NFETs106N, 108N, 110N are on simultaneously. The NFET phase Φ is assertedhigh; and the PFET phase Φ* is asserted low. The clock select circuits132, 134, responsive to CONFIG 124′, pass the respective clock phases(Φ, Φ*) to the gates 136, 138 of the top PN pair of FETs, 110N, 110P.

As can be seen from FIG. 4B, at steady state in 2:1 mode 140 CONFIG 124,124′ is low, PFET 130 is on, shunting or shorting the intermediate node122 to the supply 102. Also in 2:1 mode, the outputs 136, 138 of clockselect circuits 132, 134 are high and low, respectively, which turns offboth FETs, 110P, 110N. With both FETs, 110P, 110N off, one end 120 ofcapacitor 114 is floating, i.e., open circuited. Thus, with the end ofcapacitor 114 open circuited and the source of PFET 108P shorted to thesupply through PFET 130, the circuit 100 operates, substantiallyidentically to the 2:1 circuit 50 of FIG. 1. At steady state in 3:1 mode142 when CONFIG 124′ is high, PFET 130 is off, clock select circuits132, 134 pass the respective in-phase non-overlapping clock phases (Φ,Φ*) to PFET gates 136, 138, and the circuit 100 operates, substantiallyidentically to the 3:1 circuit 70 of FIG. 3.

FIG. 5 shows a example 150 graphing efficiency of the preferredswitched-capacitor, configurable-voltage converter circuit 100 forV_(out) in both 3:1 mode 152 and 2:1 mode 154. For this example V_(in)is 2.6V. It should be noted that although the example shown herein, isconfigurable for switching voltages between 2:1 and 3:1, it may beadapted to switching additional ratios or different ratios, e.g., byadding PN FET pairs to the totem with one or more appropriatelyconnected capacitors and control logic.

FIGS. 6A-B show an example of the clock select circuits 132, 134 withlike elements labeled identically. In this example, the clock selectcircuits 132, 134 operate primarily between the supply 102 and thevoltage at intermediate node 122. The level shifter (126 in FIG. 4A)shifts the mode select signal 124 to have a high signal level at thesupply voltage 102 and a low signal level at the intermediate voltage122. The PFET 110P clock gate 132 is essentially a pair of NAND gates150 and 152N, 154N, 152P and 154P, with the first 150 substantiallysimilar or identical to the second. Both the PFET clock phase (Φ*) andCONFIG 124′ are inputs to NAND gate 150. The output of NAND gate 150,(φ*+CONFIG)−

, is the input to the second NAND gate, i.e., FETs 152N and 154P, andCONFIG 124′ is the other input. Thus, the clock gate 132 output 136 isφ*+CONFIG−

with a high signal level at the supply voltage 102 and a low signallevel at the intermediate voltage 122 (3:2 V_(in) in this example).

The NFET 110N clock gate 134 is substantially similar to the PFET 110Pclock gate 132, except that the second NAND gate does not include gatePFET 154P. Thus, when CONFIG 124′ is low, the clock gate 134 output 138is not pulled high and floats. An inverter 156 (also between the supply102 and the voltage at intermediate node 122) inverts CONFIG 124′, todrive NFET 158. NFET 158, which is connected between the clock gate 134output 138 and V_(out) 128, NORs the second NAND result with CONFIG−

, and the result is Φ·CONFIG, with a high signal level at the supplyvoltage 102 and a low signal level at intermediate voltage 122, when 3:1mode is selected, and at V_(out) 128, when 2:1 mode is selected, whichpulls the NFET gate below its source to assure that the NFET remains off

FIG. 7 shows another example of a preferred switched-capacitor,configurable-voltage converter circuit 160, substantially similar to theexample of Figure 4A with identical elements labeled identically. Inthis example, node 122 is the configured voltage output V_(out),selectable as 3:2 or 2:1. An NFET 162 (instead of PFET 130) is gated bythe configuration selection signal 164 CONFIG−

, inverted in this example, to selectively short intermediate(configured voltage output in the example of FIG. 4A) node 128 toground. Also in this example, the configuration control 104′ isconnected between intermediate node 128 and ground, and across thebottom PN FET pair 106N, 106P. The level shifter 166, which is aninverter in this example, provides control signal CONFIG 164′ to PFET106P clock gate 132′ and NFET 106N clock gate 134′, which providesubstantially identical logic to gates 132, 134 in FIG. 4A, except atvoltage switching levels are referenced to ground.

FIG. 8 shows an example of a of an Integrated Circuit (IC) chip 170 withcircuits 172, one 174 or more of which are powered by a preferredswitched-capacitor, configurable-voltage converter circuit 176, e.g.,100 or 160. In this example 1 V_(in) is a chip supply 102, and V_(out)128 is routed to the respective circuit(s) 174.

Advantageously, a preferred switched-capacitor, configurable-voltageconverter circuit provides a low-cost, on-chip, multiple, selectablevoltage supply. In particular a preferred converter circuit providesmultiple selectable supply voltages from a single, relatively highervoltage for supplying on-chip power to lower voltage circuits. Further,because the lower voltages are capacitively switched from the highervoltage, chip supply switching currents are similarly reduced (3:1 or2:1) from on-chip switching currents. Thus, the preferred convertercircuit provides an efficient low voltage source with dramaticallyreduced chip level switching currents and associated switching noise.

While the invention has been described in terms of preferredembodiments, those skilled in the art will recognize that the inventioncan be practiced with modification within the spirit and scope of theappended claims. It is intended that all such variations andmodifications fall within the scope of the appended claims. Examples anddrawings are, accordingly, to be regarded as illustrative rather thanrestrictive.

1. A configurable-voltage converter circuit comprising: a transistor totem connected between a first supply (V_(in)) line and a second supply line; a first switching capacitor connected at one end between a first pair of totem transistors and at the opposite end between a second pair of totem transistors; a second switching capacitor connected at one end between said second pair of totem transistors and at said opposite end between a third pair of totem transistors; a configuration control selectively switching both of said third pair of totem transistors off, said opposite end of said second switching capacitor being isolated when said third pair is switched off; and a supply output between one transistor in said first pair of totem transistors and a transistor in said second pair of totem transistors, voltage on said supply output being selected by said configuration control.
 2. A configurable-voltage converter circuit as in claim 1, wherein said transistor totem is a plurality of first conduction type transistors alternating with a plurality of second conduction type transistors connected between said first supply (V_(in)) line and said second supply line, each pair of totem transistors being one of said first conduction type transistors and one of said second conduction type transistors.
 3. A configurable-voltage converter circuit as in claim 2, wherein said configuration control comprises a shunt transistor in parallel with said third pair of said totem transistors, and a pair of clock select circuits, said shunt transistor and said pair of clock select circuits being gated by a configuration select signal.
 4. A configurable-voltage converter circuit as in claim 3 receiving a pair of non-overlapping clock phases including a first phase gating first conduction type transistors and a second phase gating second conduction type transistors, wherein each phase is an input to one of said pair of clock select circuits, each clock circuit passing a respective phase responsive to said configuration select signal.
 5. A configurable-voltage converter circuit as in claim 4, wherein said second supply line is a supply return line, said configurable-voltage converter circuit is a CMOS converter, said first conduction type is N-type and said second conduction type is P-type.
 6. A configurable-voltage converter circuit as in claim 5, wherein said pair of clock select circuits comprise a PFET clock select circuit and an NFET clock select circuit passing respective clock phases responsive to said configuration signal being at a first level and blocking said respective clock phases responsive to said configuration signal being at a second level.
 7. A configurable-voltage converter circuit as in claim 6, wherein said supply output is at a first supply level when said configuration signal is at said first level, and said supply output is at a second supply level when said configuration signal is at said second level.
 8. A configurable-voltage converter circuit as in claim 7, wherein: said PFET clock select circuit comprises a pair of NAND gates, the first NAND gate NANDing a PFET clock phase with said configuration signal and said second NAND gate NANDing the output of said first NAND gate with said configuration signal; said NFET clock select circuit comprises a NAND gate NANDing an NFET clock phase with said configuration signal, an inverter and an NAND-NOR NANDing the output of said first NAND gate with said configuration signal and NORing the result with an inverted said configuration signal; and said configuration signal being high configures said configurable-voltage converter circuit in three to one (3:1) mode and said configuration signal being low configures said configurable-voltage converter circuit in three to one (2:1) mode.
 9. A configurable-voltage converter circuit as in claim 5, wherein the PFET of the third PN FET pair is connected at one conduction terminal to said first supply (V_(in)) line.
 10. A configurable-voltage converter circuit as in claim 5, wherein the NFET of the third PN FET pair is connected at one conduction terminal to said first supply return line.
 11. A CMOS configurable-voltage converter circuit comprising: a field effect transistor (FET) totem of alternate P-type FETs (PFETs) and N-type FETs (NFETs) connected between a first supply (V_(in)) line and a second supply line; a first switching capacitor connected at one end between a first PN pair of totem FETs and at the opposite end between a second PN pair of totem FETs, the first PN pair of FETs and the second PN pair of FETs being gated by a pair of non-overlapping clocks; a second switching capacitor connected at one end between said PN second pair of totem FETs and at said opposite end between a third PN pair of totem FETs; a configuration control comprising a shunt transistor in parallel with said third pair of said totem transistors gated by a configuration select signal and selectively passing said pair of non-overlapping clocks or switching both of said third PN pair of totem FETs off and said shunt transistor on, said opposite end of said second switching capacitor being isolated when the third PN FET pair is switched off; and a supply output between one FET in said first PN pair of totem FETs and an opposite type FET in said second PN pair of totem FETs, voltage on said supply output being selected by said configuration control.
 12. A CMOS configurable-voltage converter circuit as in claim 11, wherein said configuration control further comprises a pair of clock select circuits, each being one of a PFET clock select circuit and an NFET clock select circuit, each receiving one phase of said pair of non-overlapping clocks, and each being gated by said configuration select signal.
 13. A CMOS configurable-voltage converter circuit as in claim 12, wherein each phase is an input to one of said pair of clock select circuits, each clock circuit passing a respective phase responsive to said configuration select signal.
 14. A CMOS configurable-voltage converter circuit as in claim 13, wherein said PFET clock select circuit and said NFET clock select circuit pass respective clock phases responsive to said configuration signal being at a first level and block said respective clock phases responsive to said configuration signal being at a second level, said first level selecting a three to one (3:1) configuration and said second level selecting a two to one (2:1) configuration.
 15. A configurable-voltage converter circuit as in claim 14, wherein the PFET of the third PN FET pair is connected at one conduction terminal to said first supply (V_(in)) line.
 16. A configurable-voltage converter circuit as in claim 14, wherein the NFET of the third PN FET pair is connected at one conduction terminal to said second supply line.
 17. An CMOS integrated circuit (IC) chip comprising: a supply voltage line to an IC chip; a supply return line to said IC chip; a plurality of circuits on said IC chip, at least one circuit operating at a plurality of voltages lower than said supply voltage; a configurable-voltage converter circuit comprising: a field effect transistor (FET) totem of alternate P-type FETs (PFETs) and N-type FETs (NFETs) connected between a first supply line and a second supply line, said first supply line being coupled to V_(in) and said second supply line being coupled to said supply return line, a first switching capacitor connected at one end between a first PN pair of totem FETs and at the opposite end between a second PN pair of totem FETs, the first PN pair of FETs and the second PN pair of FETs being gated by a pair of non-overlapping clocks, a second switching capacitor connected at one end between said PN second pair of totem FETs and at said opposite end between a third PN pair of totem FETs, a configuration control comprising a shunt transistor in parallel with said third pair of said totem transistors gated by a configuration select signal and selectively passing said pair of non-overlapping clocks or switching both of said third PN pair of totem FETs off and said shunt transistor on, said opposite end of said second switching capacitor being isolated when the third PN FET pair is switched off, and a supply output (V_(out)) between one FET in said first PN pair of totem FETs and an opposite type FET in said second PN pair of totem FETs, voltage on said supply output being selected by said configuration control.
 18. A CMOS IC chip as in claim 17, wherein said configuration control further comprises a pair of clock select circuits, each being one of a PFET clock select circuit and an NFET clock select circuit, each receiving one phase of said pair of non-overlapping clocks, and each gated by a configuration select signal.
 19. A CMOS IC chip as in claim 18, wherein each phase is an input to one of said pair of clock select circuits, each clock circuit passing a respective phase responsive to said configuration select signal.
 20. A CMOS IC chip as in claim 19, wherein said PFET clock select circuit and said NFET clock select circuit pass respective clock phases responsive to said configuration signal being at a first level and block said respective clock phases responsive to said configuration signal being at a second level, said first level selecting a three to one (3:1) configuration and said second level selecting a two to one (2:1) configuration.
 21. A CMOS IC chip as in claim 19, wherein the PFET of the third PN FET pair is connected at one conduction terminal to said first supply (V_(in)) line.
 22. A CMOS IC chip as in claim 19, wherein the NFET of the third PN FET pair is connected at one conduction terminal to a supply return line.
 23. An CMOS integrated circuit (IC) chip comprising: a supply voltage line to an IC chip; a supply return line to said IC chip; a plurality of circuits on said IC chip, at least one circuit operating at a pair of voltages lower than said supply voltage; a configurable-voltage converter circuit, configurable between three to one (3:1) and two to one (2:1) voltage conversion, comprising: a field effect transistor (FET) totem of three P-type FETs (PFETs) and three N-type FETs (NFETs) serially connected alternating P and N FETs between a first supply line and said a second supply line, a first switching capacitor connected at one end between a first PN pair of totem FETs and at the opposite end between a second PN pair of totem FETs, the NFET of said first PN pair being further connected to said second supply line, the first PN pair of FETs and the second PN pair of FETs being gated by a pair of non-overlapping clocks, a second switching capacitor connected at one end between said PN second pair of totem FETs and at said opposite end between a third PN pair of totem FETs, the PFET of said third PN pair being further connected to first supply line, a configuration control gated by a configuration select signal and selectively passing said pair of non-overlapping clocks or switching both of said third PN pair of totem FETs off, said configuration select signal selecting between 3:1 and 2:1, said configuration select signal turning off said third PN FET pair in 2:1 mode, said third PN FET pair being gated by said pair of non-overlapping clocks in 3:1 mode, and a supply output between the PFET in said first PN pair of totem FETs and the NFET in said second PN pair of totem FETs, voltage on said supply output being selected by said configuration control.
 24. A CMOS IC chip as in claim 23, wherein said configuration control comprises a shunt PFET in parallel with said third PN pair of said totem FETs, a PFET clock select circuit and an NFET clock select circuit, each receiving one phase of said pair of non-overlapping clocks and each gated by said configuration select signal, said configuration select signal gating said shunt PFET.
 25. A CMOS IC chip as in claim 24, wherein said first supply (V_(in)) line is coupled to said supply voltage line and said second supply line is coupled to said supply return line.
 26. A configurable-voltage converter circuit as in claim 1, wherein said configuration control comprises a shunt transistor in parallel with said third pair of said totem transistors, said shunt transistor being gated by a configuration select signal. 